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altera corporation 1 max 9000 programmable logic device family june 2003, ver. 6.5 data sheet ds-m9000-6.5 includes max 9000a features... high-performance cmos eeprom-based programmable logic devices (plds) built on third-generation multiple array matrix (max ? ) architecture 5.0-v in-system programmability (isp) through built-in ieee std. 1149.1 joint test action group (jtag) interface built-in jtag boundary-scan test (bst) circuitry compliant with ieee std. 1149.1-1990 high-density erasable programmable logic device (epld) family ranging from 6,000 to 12,000 usable gates (see table 1 ) 10-ns pin-to-pin logic delays with counter frequencies of up to 144 mhz fully compliant with the peripheral component interconnect special interest group?s (pci sig) pci local bus specification, revision 2.2 dual-output macrocell for independent use of combinatorial and registered logic fasttrack ? interconnect for fast, predictable interconnect delays input/output registers with clear and clock enable on all i/o pins programmable output slew-rate control to reduce switching noise multivolt ? i/o interface operation, allowing devices to interface with 3.3-v and 5.0-v devices configurable expander product-term distribution allowing up to 32 product terms per macrocell programmable power-saving mode for more than 50 % power reduction in each macrocell table 1. max 9000 device features feature epm9320 epm9320a epm9400 epm9480 epm9560 epm9560a usable gates 6,000 8,000 10,000 12,000 flipflops 484 580 676 772 macrocells 320 400 480 560 logic array blocks (labs) 20 25 30 35 maximum user i/o pins 168 159 175 216 t pd1 (ns) 10 15 10 10 t fsu (ns) 3.0 5 3.0 3.0 t fco (ns) 4.5 7 4.8 4.8 f cnt (mhz) 144 118 144 144
2 altera corporation max 9000 programmable logic device family data sheet ...and more features programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls programmable security bit for protection of proprietary designs software design support and automatic place-and-route provided by altera?s max+plus ? ii development system on windows-based pcs as well as sun sparcstation, hp 9000 series 700/800, and ibm risc system/6000 workstations additional design entry and simulation support provided by edif 2 0 0 and 3 0 0 netlist files, library of parameterized modules (lpm), verilog hdl, vhdl, and other interfaces to popular eda tools from manufacturers such as cadence, exemplar logic, mentor graphics, orcad, synopsys, synplicity, and veribest programming support with altera?s master programming unit (mpu), bitblaster tm serial download cable, byteblaster tm parallel port download cable, and byteblastermv tm parallel port download cable, as well as programming hardware from third-party manufacturers offered in a variety of package options with 84 to 356 pins (see table 2 ) notes: (1) max 9000 device package types include plastic j-lead chip carrier (plcc), power quad flat pack (rqfp), ceramic pin-grid array (pga), and ball-grid array (bga) packages. (2) perform a complete thermal analysis before committing a design to this device package. see application note 74 (evaluating power for altera devices) . table 2. max 9000 package options & i/o counts note (1) device 84-pin plcc 208-pin rqfp 240-pin rqfp 280-pin pga 304-pin rqfp 356-pin bga epm9320 60 (2) 132 e 168 e 168 epm9320a 60 (2) 132eee168 epm9400 59 (2) 139 159 e e e epm9480 e 146 175 e e e epm9560 e 153 191 216 216 216 epm9560a e 153 191 e e 216
altera corporation 3 max 9000 programmable logic device family data sheet general description the max 9000 family of in-system-programmable, high-density, high- performance eplds is based on altera?s third-generation max architecture. fabricated on an advanced cmos technology, the eeprom- based max 9000 family provides 6,000 to 12,000 usable gates, pin-to-pin delays as fast as 10 ns, and counter speeds of up to 144 mhz. the -10 speed grade of the max 9000 family is compliant with the pci local bus specification, revision 2.2 . table 3 shows the speed grades available for max 9000 devices. ta bl e 4 shows the performance of max 9000 devices for typical functions. note: (1) internal logic array block (lab) performance is shown. numbers in parentheses show external delays from row input pin to row i/o pin. the max 9000 architecture supports high-density integration of system- level logic functions. it easily in tegrates multiple programmable logic devices ranging from pals, gals, and 22v10s to field-programmable gate array (fpga) devices and eplds. table 3. max 9000 speed grade availability device speed grade -10 -15 -20 epm9320 vv v vv vv vv v f note (1) application macrocells used speed grade units -10 -15 -20 16-bit loadable counter 16 144 118 100 mhz 16-bit up/down counter 16 144 118 100 mhz 16-bit prescaled counter 16 144 118 100 mhz 16-bit address decode 1 5.6 (10) 7.9 (15) 10 (20) ns 16-to-1 multiplexer 1 7.7 (12.1) 10.9 (18) 16 (26) ns
4 altera corporation max 9000 programmable logic device family data sheet all max 9000 device packages provide four dedicated inputs for global control signals with large fan-outs. each i/o pin has an associated i/o cell register with a clock enable control on the periphery of the device. as outputs, these registers provide fast clock-to-output times; as inputs, they offer quick setup times. max 9000 eplds provide 5.0-v in-system programmability (isp). this feature allows the devices to be programmed and reprogrammed on the printed circuit board (pcb) for quick and efficient iterations during design development and debug cycles. max 9000 devices are guaranteed for 100 program and erase cycles. max 9000 eplds contain 320 to 560 macrocells that are combined into groups of 16 macrocells, called logic array blocks (labs). each macrocell has a programmable- and /fixed- or array and a configurable register with independently programmable clock, clock enable, clear, and preset functions. for increased flexibility, each macrocell offers a dual-output structure that allows the register and the product terms to be used independently. this feature allows register-rich and combinatorial- intensive designs to be implemented efficiently. the dual-output structure of the max 9000 macrocell also improves logic utilization, thus increasing the effective capacity of the devices. to build complex logic functions, each macrocell can be supplemented with both shareable expander product terms and high-speed parallel expander product terms to provide up to 32 product terms per macrocell. the max 9000 family provides programmable speed/power optimization. speed-critical portions of a design can run at high speed/full power, while the remaining portions run at reduced speed/low power. this speed/power optimization feature enables the user to configure one or more macrocells to operate at 50 % or less power while adding only a nominal timing delay. max 9000 devices also provide an option that reduces the slew rate of the output buffers, minimizing noise transients when non-speed-critical signals are switching. max 9000 devices offer the multivolt feature, which allows output drivers to be set for either 3.3-v or 5.0-v operation in mixed- voltage systems.
altera corporation 5 max 9000 programmable logic device family data sheet the max 9000 family is supported by altera?s max+plus ii development system, a single, integrated software package that offers schematic, text?including vhdl, verilog hdl, and the altera hardware description language (ahdl)?and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. the max+plus ii software provides edif 2 0 0 and 3 0 0, lpm, and other interfaces for additional design entry and simulation support from other industry-standard pc- and unix- workstation-based eda tools. the max+plus ii software runs on windows-based pcs as well as sun sparcstation, hp 9000 series 700/800, and ibm risc system/6000 workstations. f fv max+plus ii programmable logic development system & software data sheet . functional description max 9000 devices use a third-generation max architecture that yields both high performance and a high degree of utilization for most applications. the max 9000 architecture includes the following elements: logic array blocks macrocells expander product terms (shareable and parallel) fasttrack interconnect dedicated inputs i/o cells figure 1 shows a block diagram of the max 9000 architecture.
6 altera corporation max 9000 programmable logic device family data sheet figure 1. max 9000 device block diagram logic array blocks the max 9000 architecture is based on linking high-performance, flexible logic array modules called logic array blocks (labs). labs consist of 16-macrocell arrays that are fed by the lab local array, as shown in figure 2 on page 7 . multiple labs are linked together via the fasttrack interconnect, a series of fast, continuous channels that run the entire length and width of the device. the i/o pins are supported by i/o cells (iocs) located at the end of each row (horizontal) and column (vertical) path of the fasttrack interconnect. each lab is fed by 33 inputs from the row interconnect and 16 feedback signals from the macrocells within the lab. all of these signals are available within the lab in their true and inverted form. in addition, 16 shared expander product terms (?expanders?) are available in their inverted form, for a total of 114 signals that feed each product term in the lab. each lab is also fed by two low-skew global clocks and one global clear that can be used for register control signals in all 16 macrocells. ioc ioc io c io c io c io c ioc ioc ioc ioc ioc ioc ioc ioc i/o cell (ioc) logic array block (lab) macrocell fasttrack interconnect ioc ioc lab local array
altera corporation 7 max 9000 programmable logic device family data sheet labs drive the row and column interconnect directly. each macrocell can drive out of the lab onto one or both routing resources. once on the row or column interconnect, signals can traverse to other labs or to the iocs. figure 2. max 9000 logic array block column fasttrac k interconnect row fasttrack interconnect 33 48 to peripheral bus and other labs in the device global control select din2 gclr 16 16 48 see figure 7 for details. macrocell 1 macrocell 2 macrocell 3 macrocell 4 macrocell 5 macrocell 6 macrocell 7 macrocell 8 lab local array (114 channels) shared expander signals local feedback 16 16 16 gclk1 gclk2 16 din3 din4 goe to peripheral bus din1 macrocell 9 macrocell 10 macrocell 11 macrocell 12 macrocell 13 macrocell 14 macrocell 15 macrocell 16
8 altera corporation max 9000 programmable logic device family data sheet macrocells the max 9000 macrocell consists of three functional blocks: the product terms, the product-term select matrix, and the programmable register. the macrocell can be individually configured for both sequential and combinatorial logic operation. see figure 3 . figure 3. max 9000 macrocell & local array combinatorial logic is implemented in the local array, which provides five product terms per macrocell. the product-term select matrix allocates these product terms for use as either primary logic inputs (to the or and xor gates) to implement combinatorial functions, or as secondary inputs to the macrocell?s register clear, preset, clock, and clock enable control functions. two kinds of expander product terms (?expanders?) are available to supplement macrocell logic resources: shareable expanders, which are inverted product terms that are fed back into the logic array parallel expanders, which are product terms borrowed from adjacent macrocells the max+plus ii software automatically optimizes product-term allocation according to the logic requirements of the design. vcc product- term select matrix 16 local feedbacks 16 shareable expander product lab local array parallel expanders (from other macrocells) clear select global clear global clocks clock/ enable select 2 prn clrn d/t q ena register bypass to row or column fasttrack interconnect programmable register macrocell input select local array feedback 33 row fasttrack interconnect inputs
altera corporation 9 max 9000 programmable logic device family data sheet for registered functions, each macrocell register can be individually programmed for d, t, jk, or sr operation with programmable clock control. the flipflop can also be bypassed for combinatorial operation. during design entry, the user specifies the desired register type; the max+plus ii software then selects the most efficient register operation for each registered function to optimize resource utilization. each programmable register can be clocked in three different modes: by either global clock signal. this mode achieves the fastest clock-to- output performance. by a global clock signal and enabled by an active-high clock enable. this mode provides an enable on each flipflop while still achieving the fast clock-to-output performance of the global clock. by an array clock implemented with a product term. in this mode, the flipflop can be clocked by signals from buried macrocells or i/o pins. two global clock signals are available. as shown in figure 2 , these global clock signals can be the true or the complement of either of the global clock pins ( din1 and din2 ). each register also supports asynchronous preset and clear functions. as shown in figure 3 , the product-term select matrix allocates product terms to control these operations. although the product-term-driven preset and clear inputs to registers are active high, active-low control can be obtained by inverting the signal within the logic array. in addition, each register clear function can be individually driven by the dedicated global clear pin ( din3 ). the global clear can be programmed for active-high or active-low operation. all max 9000 macrocells offer a dual-output structure that provides independent register and combinatorial logic output within the same macrocell. this function is implemented by a process called register packing. when register packing is used, the product-term select matrix allocates one product term to the d input of the register, while the remaining product terms can be used to implement unrelated combinatorial logic. both the registered and the combinatorial output of the macrocell can feed either the fasttrack interconnect or the lab local array.
10 altera corporation max 9000 programmable logic device family data sheet expander product terms although most logic functions can be implemented with the five product terms available in each macrocell, some logic functions are more complex and require additional product terms. although another macrocell can supply the required logic resources, the max 9000 architecture also offers both shareable and parallel expander product terms that provide additional product terms directly to any macrocell in the same lab. these expanders help ensure that logic is synthesized with the fewest possible logic resources to obtain the fastest possible speed. shareable expanders each lab has 16 shareable expanders that can be viewed as a pool of uncommitted single product terms (one from each macrocell) with inverted outputs that feed back into the lab local array. each shareable expander can be used and shared by any or all macrocells in the lab to build complex logic functions. a small delay ( t local + t sexp ) is incurred when shareable expanders are used. figure 4 shows how shareable expanders can feed multiple macrocells. figure 4. max 9000 shareable expanders macrocell product-term logic product-term select matrix macrocell product-term logic lab local array 16 local feedbacks 16 shared expanders 33 row fasttrack interconnect signals shareable expanders can be shared by any or all macrocells in the lab.
altera corporation 11 max 9000 programmable logic device family data sheet parallel expanders parallel expanders are unused product terms that can be allocated to a neighboring macrocell to implement fast, complex logic functions. parallel expanders allow up to 20 product terms to directly feed the macrocell or logic, with five product terms provided by the macrocell and 15 parallel expanders provided by neighboring macrocells in the lab. figure 5 shows how parallel expanders can feed the neighboring macrocell. figure 5. max 9000 parallel expanders preset clock clear product- te r m select matrix preset clock clear product- te r m select matrix macrocell product- term logic from previous macrocell to next macrocell lab local array macrocell product- term logic 33 row fasttrack interconnect signals 16 local feedbacks 16 shared expanders unused product terms in a macrocell can be allocated to a neighboring macrocell.
12 altera corporation max 9000 programmable logic device family data sheet the max+plus ii compiler automatically allocates as many as three sets of up to five parallel expanders to macrocells that require additional product terms. each set of expanders incurs a small, incremental timing delay ( t pexp ). for example, if a macrocell requires 14 product terms, the compiler uses the five dedicated product terms within the macrocell and allocates two sets of parallel expanders; the first set includes five product terms and the second set includes four product terms, increasing the total delay by 2 t pexp . two groups of eight macrocells within each lab (e.g., macrocells 1 through 8 and 9 through 16) form two chains to lend or borrow parallel expanders. a macrocell borrows parallel expanders from lower- numbered macrocells. for example, macrocell 8 can borrow parallel expanders from macrocell 7, from macrocells 7 and 6, or from macrocells 7, 6, and 5. within each group of 8, the lowest-numbered macrocell can only lend parallel expanders and the highest-numbered macrocell can only borrow them. fasttrack interconnect in the max 9000 architecture, connections between macrocells and device i/o pins are provided by the fasttrack interconnect, a series of continuous horizontal and vertical routing channels that traverse the entire device. this device-wide routing structure provides predictable performance even in complex designs. in contrast, the segmented routing in fpgas requires switch matrices to connect a variable number of routing paths, increasing the delays between logic resources and reducing performance. figure 6 shows the interconnection of four adjacent labs with row and column interconnects.
altera corporation 13 max 9000 programmable logic device family data sheet figure 6. max 9000 device interconnect resources the labs within max 9000 devices are arranged into a matrix of columns and rows. table 5 shows the number of columns and rows in each max 9000 device. each lab is named on the basis of its physical row (a, b, c, etc.) and column (1, 2, 3, etc.) position within the device. lab a1 lab a2 lab b1 lab b2 column fasttrack interconnect row fasttrack interconnect see figure 8 for details. see figure 9 for details. ioc1 ioc10 ioc1 ioc10 ioc1 ioc8 ioc1 ioc8 ioc1 ioc10 ioc1 ioc10 ioc1 ioc8 ioc1 ioc8 see figure 7 for details. table 5. max 9000 rows & columns devices rows columns epm9320, epm9320a 4 5 epm9400 5 5 epm9480 6 5 epm9560, epm9560a 7 5
14 altera corporation max 9000 programmable logic device family data sheet each row of labs has a dedicated row interconnect that routes signals both into and out of the labs in the row. the row interconnect can then drive i/o pins or feed other labs in the device. each row interconnect has a total of 96 channels. figure 7 shows how a macrocell drives the row and column interconnect. figure 7. max 9000 lab connections to row & column interconnect each macrocell in the lab can drive one of three separate column interconnect channels. the column channels run vertically across the entire device, and are shared by the macrocells in the same column. the max+plus ii compiler optimizes connections to a column channel automatically. macrocell 1 macrocell 2 96 row channels 48 column channels each macrocell drives one of three column channels . to lab local array each macrocell drives one row channel. additional multiplexer provides column-to-row path if macrocell drives row channel. dual-output macrocell feeds both fasttrack interconnect and lab local array. lab
altera corporation 15 max 9000 programmable logic device family data sheet a row interconnect channel can be fed by the output of the macrocell through a 4-to-1 multiplexer that the macrocell shares with three column channels. if the multiplexer is used for a macrocell-to-row connection, the three column signals can access another row channel via an additional 3-to-1 multiplexer. within any lab, the multiplexers provide all 48 column channels with access to 32 row channels. row-to-i/o cell connections figure 8 illustrates the connections between row interconnect channels and iocs. an input signal from an ioc can drive two separate row channels. when an ioc is used as an output, the signal is driven by a 10-to-1 multiplexer that selects the row channels. each end of the row channel feeds up to eight iocs on the periphery of the device. figure 8. max 9000 row-to-ioc connections column-to-i/o cell connections each end of a column channel has up to 10 iocs (see figure 9 ). an input signal from an ioc can drive two separate column channels. when an ioc is used as an output, the signal is driven by a 17-to-1 multiplexer that selects the column channels. 96 96 each ioc is driven by a 10-to-1 multiplexer. each ioc can drive up to two row channels. ioc8 ioc1 10 10 row fasttrack interconnect 96
16 altera corporation max 9000 programmable logic device family data sheet figure 9. max 9000 column-to-ioc connections dedicated inputs in addition to the general-purpose i/o pins, max 9000 devices have four dedicated input pins. these dedicated inputs provide low-skew, device- wide signal distribution to the labs and iocs in the device, and are typically used for global clock, clear, and output enable control signals. the global control signals can feed the macrocell or ioc clock and clear inputs, as well as the ioc output enable. the dedicated inputs can also be used as general-purpose data inputs because they can feed the row fasttrack interconnect (see figure 2 on page 7 ). i/o cells figure 10 shows the ioc block diagram. signals enter the max 9000 device from either the i/o pins that provide general-purpose input capability or from the four dedicated inputs. the iocs are located at the ends of the row and column interconnect channels. 48 each ioc is driven by a 17-to-1 multiplexer. each ioc can drive u p to two column channels. 17 17 column fastt rack interconnect ioc10 ioc1 48 48
altera corporation 17 max 9000 programmable logic device family data sheet figure 10. max 9000 ioc i/o pins can be used as input, output, or bidirectional pins. each ioc has an ioc register with a clock enable input. this register can be used either as an input register for external data that requires fast setup times, or as an output register for data that requires fast clock-to-output performance. the ioc register clock enable allows the global clock to be used for fast clock-to-output performance, while maintaining the flexibility required for selective clocking. the clock, clock enable, clear, and output enable controls for the iocs are provided by a network of i/o control signals. these signals can be supplied by either the dedicated input pins or internal logic. the ioc control-signal paths are designed to minimize the skew across the device. all control-signal sources are buffered onto high-speed drivers that drive the signals around the periphery of the device. this ?peripheral bus? can be configured to provide up to eight output enable signals, up to four clock signals, up to six clock enable signals, and up to two clear signals. table 6 on page 18 shows the sources that drive the peripheral bus and how the ioc control signals share the peripheral bus. slew-rate control from row or column fasttrack interconnect 4 2 8 13 to row or column fasttrack interconnect oe [7..0] clk [3..0] ena [5..0] clr [1..0] peripheral control bus [12..0] clrn dq ena vcc vcc 6 vcc
18 altera corporation max 9000 programmable logic device family data sheet the output buffer in each ioc has an adjustable output slew rate that can be configured for low-noise or high-speed performance. a slower slew rate reduces board-level noise and adds a nominal timing delay to the output buffer delay ( t od ) parameter. the fast slew rate should be used for speed-critical outputs in systems that are adequately protected against noise. designers can specify the slew rate on a pin-by-pin basis during design entry or assign a default slew rate to all pins on a global basis. the slew rate control affects both rising and falling edges of the output signals. output configuration the max 9000 device architecture supports the multivolt i/o interface feature, which allows max 9000 devices to interface with systems of differing supply voltages. the 5.0-v devices in all packages can be set for 3.3-v or 5.0-v i/o pin operation. these devices have one set of v cc pins for internal operation and input buffers ( vccint ), and another set for i/o output drivers ( vccio ). the vccint pins must always be connected to a 5.0-v power supply. with a 5.0-v v ccint level, input voltages are at ttl levels and are therefore compatible with 3.3-v and 5.0-v inputs. table 6. peripheral bus sources peripheral control signal source epm9320 epm9320a epm9400 epm9480 epm9560 epm9560a oe0/ena0 row c row e row f row g oe1/ena1 row b row e row f row f oe2/ena2 row arow erow erow e oe3/ena3 row brow brow brow b oe4/ena4 row arow arow arow a oe5 row drow drow drow d oe6 row crow crow crow c oe7/clr1 row b/ goe row b/ goe row b/ goe row b/ goe clr0/ena5 row a/ gclr row a/ gclr row a/ gclr row a/ gclr clk0 gclk1 gclk1 gclk1 gclk1 clk1 gclk2 gclk2 gclk2 gclk2 clk2 row drow drow drow d clk3 row crow crow crow c
altera corporation 19 max 9000 programmable logic device family data sheet the vccio pins can be connected to either a 3.3-v or 5.0-v power supply, depending on the output requirements. when the vccio pins are connected to a 5.0-v power supply, the output levels are compatible with 5.0-v systems. when the vccio pins are connected to a 3.3-v power supply, the output high is at 3.3 v and is therefore compatible with 3.3-v or 5.0-v systems. devices operating with v ccio levels lower than 4.75 v incur a nominally greater timing delay of t od2 instead of t od1 . in-system programma- bility (isp) max 9000 devices can be programmed in-system through a 4-pin jtag interface. isp offers quick and efficient iterations during design development and debug cycles. the max 9000 architecture internally generates the 12.0-v programming voltage required to program eeprom cells, eliminating the need for an external 12.0-v power supply to program the devices on the board. during isp, the i/o pins are tri-stated to eliminate board conflicts. isp simplifies the manufacturing flow by allowing the devices to be mounted on a printed circuit board with standard pick-and-place equipment before they are programmed. max 9000 devices can be programmed by downloading the information via in-circuit testers, embedded processors, or the altera bitblaster, byteblaster, or byteblastermv download cable. (the byteblaster cable is obsolete and has been replaced by the byteblastermv cable, which can interface with 2.5-v, 3.3-v, and 5.0-v devices.) programming the devices after they are placed on the board eliminates lead damage on high pin-count packages (e.g., qfp packages) due to device handling. max 9000 devices can also be reprogrammed in the field (i.e., product upgrades can be performed in the field via software or modem). in-system programming can be accomplished with either an adaptive or constant algorithm. an adaptive algorithm reads information from the unit and adapts subsequent programming steps to achieve the fastest possible programming time for that unit. because some in-circuit testers platforms have difficulties supporting an adaptive algorithm, altera offers devices tested with a consta nt algorithm. devices tested to the constant algorithm have an ?f? suffix in the ordering code.
20 altera corporation max 9000 programmable logic device family data sheet programming sequence during in-system programming, instructions, addresses, and data are shifted into the max 9000 device through the tdi input pin. data is shifted out through the tdo output pin and compared against the expected data. programming a pattern into the device requires the following six isp stages. a stand-alone verification of a programmed pattern involves only stages 1, 2, 5, and 6. 1. enter isp . the enter isp stage ensures that the i/o pins transition smoothly from user mode to isp mode. the enter isp stage requires 1ms. 2. check id . before any program or verify process, the silicon id is checked. the time required to read this silicon id is relatively small compared to the overall programming time. 3. bulk erase . erasing the device in-system involves shifting in the instructions to erase the device and applying one erase pulse of 100 ms. 4. program . programming the device in-system involves shifting in the address and data and then applying the programming pulse to program the eeprom cells. this process is repeated for each eeprom address. 5. verify . verifying an altera device in-system involves shifting in addresses, applying the read pulse to verify the eeprom cells, and shifting out the data for comparison. this process is repeated for each eeprom address. 6. exit isp . an exit isp stage ensures that the i/o pins transition smoothly from isp mode to user mode. the exit isp stage requires 1ms. programming times the time required to implement each of the six programming stages can be broken into the following two elements: a pulse time to erase, program, or read the eeprom cells. a shifting time based on the test clock ( tck ) frequency and the number of tck cycles to shift instructions, address, and data into the device.
altera corporation 21 max 9000 programmable logic device family data sheet by combining the pulse and shift times for each of the programming stages, the program or verify time can be derived as a function of the tck frequency, the number of devices, and specific target device(s). because different isp-capable devices have a different number of eeprom cells, both the total fixed and total variable times are unique for a single device. programming a single max 9000 device the time required to program a single max 9000 device in-system can be calculated from the following formula: where: t prog = programming time t ppulse = sum of the fixed times to erase, program, and verify the eeprom cells cycle ptck =number of tck cycles to program a device f tck = tck frequency the isp times for a stand-alone verification of a single max 9000 device can be calculated from the following formula: where: t ver =verify time t vpulse = sum of the fixed times to verify the eeprom cells cycle vtck =number of tck cycles to verify a device t prog t ppulse cycle ptc k f tck ----------------------------- -- - + = t ver t vpulse cycle vtc k f tck ----------------------------- --- + =
22 altera corporation max 9000 programmable logic device family data sheet the programming times described in tables 7 through 9 are associated with the worst-case method using the isp algorithm. tables 8 and 9 show the in-system programming and stand alone verification times for several common test clock frequencies. table 7. max 9000 t pulse & cycle tck values device programming stand-alone verification t ppulse (s) cycle ptck t vpulse (s) cycle vtck epm9320 epm9320a 11.79 2,966,000 0.15 1,806,000 epm9400 12.00 3,365,000 0.15 2,090,000 epm9480 12.21 3,764,000 0.15 2,374,000 epm9560 epm9560a 12.42 4,164,000 0.15 2,658,000 table 8. max 9000 in-system programming times for different test clock frequencies device f tck units 10 mhz 5 mhz 2 mhz 1 mhz 500 khz 200 khz 100 khz 50 khz epm9320 epm9320a 12.09 12.38 13.27 14.76 17.72 26.62 41.45 71.11 s epm9400 12.34 12.67 13.68 15.37 18.73 28.83 45.65 79.30 s epm9480 12.59 12.96 14.09 15.98 19.74 31.03 49.85 87.49 s epm9560 epm9560a 12.84 13.26 14.50 16.59 20.75 33.24 54.06 95.70 s table 9. max 9000 stand-alone verification times for different test clock frequencies device f tck units 10 mhz 5 mhz 2 mhz 1 mhz 500 khz 200 khz 100 khz 50 khz epm9320 epm9320a 0.33 0.52 1.06 1.96 3.77 9.18 18.21 36.27 s epm9400 0.36 0.57 1.20 2.24 4.33 10.60 21.05 41.95 s epm9480 0.39 0.63 1.34 2.53 4.90 12.02 23.89 47.63 s epm9560 epm9560a 0.42 0.69 1.48 2.81 5.47 13.44 26.73 53.31 s
altera corporation 23 max 9000 programmable logic device family data sheet programming with external hardware max 9000 devices can be programmed on windows-based pcs with an altera logic programmer card, the master programming unit (mpu), and the appropriate device adapter. the mpu performs continuity checking to ensure adequate electrical contact between the adapter and the device. f f altera programming hardware data sheet . the max+plus ii software can use text- or waveform-format test vectors created with the max+plus ii text editor or waveform editor to test a programmed device. for added design verification, designers can perform functional testing to compare the functional behavior of a max 9000 device with the results of simulation. data i/o, bp microsystems, and other programming hardware manufacturers also provide programming support for altera devices. f f programming hardware manufacturers . ieee std. 1149.1 (jtag) boundary-scan support max 9000 devices support jtag bst circuitry as specified by ieee std. 1149.1-1990. table 10 describes the jtag instructions supported by the max 9000 family. the pin-out tables starting on page 38 show the location of the jtag control pins for each device. if the jtag interface is not required, the jtag pins are available as user i/o pins. table 10. max 9000 jtag instructions jtag instruction description sample/preload allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern output at the device pins. extest allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. bypass places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through a selected device to adjacent devices during normal device operation. idcode selects the idcode register and places it between tdi and tdo , allowing the idcode to be shifted out of tdo . supported by the epm9320a, epm9400, epm9480, and epm9560a devices only. uescode selects the user electronic signature (uescode) register and allows the uescode to be shifted out of tdo serially. this instruction is supported by max 9000a devices only. isp instructions these instructions are used when programming max 9000 devices via the jtag ports with the bitblaster or byteblastermv download cable, or using a jam file ( .jam ), jam byte-code file ( .jbc ), or serial vector format ( .svf ) file via an embedded processor or test equipment.
24 altera corporation max 9000 programmable logic device family data sheet the instruction register length for max 9000 devices is 10 bits. epm9320a and epm9560a devices support a 16-bit uescode register. tables 11 and 12 show the boundary-scan register length and device idcode information for max 9000 devices. notes: (1) the idcode?s least significant bit (lsb) is always 1 . (2) the most significant bit (msb) is on the left. (3) although the epm9320a and epm9560a devices support the idcode instruction, the epm9320 and epm9560 devices do not. figure 11 shows the timing requirements for the jtag signals. table 11. max 9000 boundary-scan register length device boundary-scan register length epm9320, epm9320a 504 epm9400 552 epm9480 600 epm9560, epm9560a 648 table 12. 32-bit max 9000 device idcode note (1) device idcode (32 bits) version (4 bits) part number (16 bits) (2) manufacturer?s identity (11 bits) 1 (1 bit) epm9320a (3) 0000 1001 0011 0010 0000 00001101110 1 epm9400 0000 1001 0100 0000 0000 00001101110 1 epm9480 0000 1001 0100 1000 0000 00001101110 1 epm9560a (3) 0000 1001 0101 0110 0000 00001101110 1
altera corporation 25 max 9000 programmable logic device family data sheet figure 11. max 9000 jtag waveforms table 13 shows the jtag timing parameters and values for max 9000 devices. f f vf application note 39 (ieee 1149.1 (jtag) boundary-scan testing in altera devices) . table 13. jtag timing parameters & values for max 9000 devices symbol parameter min max unit t jcp tck clock period 100 ns t jch tck clock high time 50 ns t jcl tck clock low time 50 ns t jpsu jtag port setup time 20 ns t jph jtag port hold time 45 ns t jpco jtag port clock to output 25 ns t jpzx jtag port high impedance to valid output 25 ns t jpxz jtag port valid output to high impedance 25 ns t jssu capture register setup time 20 ns t jsh capture register hold time 45 ns t jsco update register clock to output 25 ns t jszx update register high impedance to valid output 25 ns t jsxz update register valid output to high impedance 25 ns tdo tck t jpzx t jpco t jph t jpxz t jcp t jpsu t jcl t jch tdi tms signal to be captured signal to be driven t jszx t jssu t jsh t jsco t jsxz
26 altera corporation max 9000 programmable logic device family data sheet programmable speed/power control max 9000 devices offer a power-saving mode that supports low-power operation across user-defined signal paths or the entire device. because most logic applications require only a small fraction of all gates to operate at maximum frequency, this feature allows total power dissipation to be reduced by 50 % or more. the designer can program each individual macrocell in a max 9000 device for either high-speed (i.e., with the turbo bit ? option turned on) or low-power (i.e., with the turbo bit option turned off) operation. as a result, speed-critical paths in the design can run at high speed, while remaining paths operate at reduced power. macrocells that run at low power incur a nominal timing delay adder ( t lpa ) for the lab local array delay ( t local ). design security all max 9000 eplds contain a programmable security bit that controls access to the data programmed into the device. when this bit is programmed, a proprietary design implemented in the device cannot be copied or retrieved. this feature provides a high level of design security, because programmed data within eeprom cells is invisible. the security bit that controls this function, as well as all other programmed data, is reset only when the device is erased. generic testing max 9000 eplds are fully functionally tested. complete testing of each programmable eeprom bit and all logic functionality ensures 100 % programming yield. ac test measurements are taken under conditions equivalent to those shown in figure 12 . test patterns can be used and then erased during the early stages of the production flow. figure 12. max 9000 ac test conditions vcc to test system c1 (includes jig capacitance ) device input rise and fall times < 3 ns device output 464 ? ? ? ? power supply transients can affect ac measurements. simultaneous transitions of multiple outputs should be avoided for accurate measurement. threshold tests must not be performed under ac conditions. large-amplitude, fast ground- current transients normally occur as the device outputs discharge the load capacitances. when these transients flow through the parasitic inductance between the device ground pin and the test system ground, significant reductions in observable noise immunity can result. numbers in parentheses are for 3.3-v outputs. numbers without parentheses are for 5.0-v devices or outputs.
altera corporation 27 max 9000 programmable logic device family data sheet operating conditions tables 14 through 20 provide information on absolute maximum ratings, recommended operating conditions, operating conditions, and capacitance for max 9000 devices. table 14. max 9000 device absolute maximum ratings note (1) symbol parameter conditions min max unit v cc supply voltage with respect to ground (2) e2.0 7.0 v v i dc input voltage e2.0 7.0 v v ccisp supply voltage during in-system programming e2.0 7.0 v i out dc output current, per pin e25 25 ma t stg storage temperature no bias e65 150 (3) , (4) 4.75 (4.50) 5.25 (5.50) v v ccio supply voltage for output drivers, 5.0-v operation (3) , (4) 4.75 (4.50) 5.25 (5.50) v supply voltage for output drivers, 3.3-v operation (3) , (4) 3.00 (3.00) 3.60 (3.60) v v ccisp supply voltage during in-system programming 4.75 5.25 v v i input voltage e0.5 v ccint + 0.5 v v o output voltage 0v ccio v t a ambient temperature for commercial use 0 70
28 altera corporation max 9000 programmable logic device family data sheet table 16. max 9000 device dc operating conditions notes (5) , (6) symbol parameter conditions min max unit v ih high-level input voltage (7) 2.0 v ccint + 0.5 v v il low-level input voltage e0.5 0.8 v v oh 5.0-v high-level ttl output voltage i oh = e4 ma dc, v ccio = 4.75 v (8) 2.4 v 3.3-v high-level ttl output voltage i oh = e4 ma dc, v ccio = 3.00 v (8) 2.4 v 3.3-v high-level cmos output voltage i oh = e0.1 ma dc, v ccio = 3.00 v (8) v ccio e 0.2 v v ol 5.0-v low level ttl output voltage i ol = 12 ma dc, v ccio = 4.75 v (8) 0.45 v 3.3-v low-level ttl output voltage i ol = 12 ma dc, v ccio = 3.00 v (8) 0.45 v 3.3-v low-level cmos output voltage i ol = 0.1 ma dc, v ccio = 3.00 v (8) 0.2 v i i i/o pin leakage current of dedicated input pins v i = e0.5 to 5.5 v (9) e10 10 note (10) symbol parameter conditions min max unit c din1 dedicated input capacitance v in = 0 v, f = 1.0 mhz 18 pf c din2 dedicated input capacitance v in = 0 v, f = 1.0 mhz 18 pf c din3 dedicated input capacitance v in = 0 v, f = 1.0 mhz 17 pf c din4 dedicated input capacitance v in = 0 v, f = 1.0 mhz 20 pf c i/o i/o pin capacitance v in = 0 v, f = 1.0 mhz 12 pf table 18. max 9000a device capacitance: epm9320a & epm9560a devices note (10) symbol parameter conditions min max unit c din1 dedicated input capacitance v in = 0 v, f = 1.0 mhz 16 pf c din2 dedicated input capacitance v in = 0 v, f = 1.0 mhz 10 pf c din3 dedicated input capacitance v in = 0 v, f = 1.0 mhz 10 pf c din4 dedicated input capacitance v in = 0 v, f = 1.0 mhz 12 pf c i/o i/o pin capacitance v in = 0 v, f = 1.0 mhz 8 pf table 19. max 9000 device typical i cc supply current values symbol parameter conditions epm9320 epm9400 epm9480 epm9560 unit i cc1 i cc supply current (low-power mode, standby, typical) v i = ground, no load (11) 106 132 140 146 ma
altera corporation 29 max 9000 programmable logic device family data sheet notes to tables: (1) see the operating requirements for altera devices data sheet . (2) minimum dc input on i/o pins is ?0.5 v and on the four dedicated input pins is ?0.3 v. during transitions, the inputs may undershoot to ?2.0 v or overshoot to 7.0 v for periods shorter than 20 ns under no-load conditions. (3) v cc must rise monotonically. (4) numbers in parentheses are for industrial-temperature-range devices. (5) typical values are for t a = 25 tck pin is 3.6 v. the minimum v ih of this pin during jtag testing remains at 2.0 v. to attain this 3.6-v v ih during programming, the byteblaster and byteblastermv download cables must have a 5.0-v v cc . (8) this parameter is measured with 50 % of the outputs each sinking 12 ma. the i oh parameter refers to high-level ttl or cmos output current; the i ol parameter refers to the low-level ttl or cmos output current. (9) jtag pin input leakage is typically ?60 ? note (1) note: (1) output drive characteristics include the jtag tdo pin. table 20. max 9000a device typical i cc supply current values symbol parameter conditions epm9320a epm9560a unit i cc1 i cc supply current (low-power mode, standby, typical) v i = ground, no load (11) 99 174 ma 12345 30 60 90 150 120 v ccio = 5.0 v i ol i oh room temperature 12345 30 60 90 150 120 v ccio = 3.3 v i ol i oh room temperature 3.3 t ypical i o utput c urrent (ma) output voltage (v) output voltage (v) o typical i output current (ma) o 5.0-v 3.3-v
30 altera corporation max 9000 programmable logic device family data sheet timing model the continuous, high-performance fasttrack interconnect ensures predictable performance and accurate simulation and timing analysis. this predictable performance contrasts with that of fpgas, which use a segmented connection scheme and hence have unpredictable performance. timing simulation and delay prediction are available with the max+plus ii simulator and timing analyzer, or with industry- standard eda tools. the simulator offers both pre-synthesis functional simulation to evaluate logic design accuracy and post-synthesis timing simulation with 0.1-ns resolution. the timing analyzer provides point- to-point timing delay information, setup and hold time prediction, and device-wide performance analysis. the max 9000 timing model in figure 14 shows the delays that correspond to various paths and functions in the circuit. this model contains three distinct parts: the macrocell, ioc, and interconnect, including the row and column fasttrack interconnect and lab local array paths. each parameter shown in figure 14 is expressed as a worst-case value in the internal timing characteristics tables in this data sheet. hand- calculations that use the max 9000 timing model and these timing parameters can be used to estimate max 9000 device performance. f f application note 77 (understanding max 9000 timing) .
altera corporation 31 max 9000 programmable logic device family data sheet figure 14. max 9000 timing model macrocell t rd t comb t su t h t pre t clr macrocell/ register delays logic array delay t lad register control delay shared expander delay t sexp global input delays i/o pi n t inreg t iodr t iodc i/o register delays output data delay i/o cell control delay input delay output delays t iord t iocomb t iosu t ioh t ioclr t od1 t od2 t od3 t xz t zx1 t zx2 t zx3 ioc t col t row t local parallel expander delay t pexp t din_d t din_clk t din_clr t din_io t din_ioc fasttrack drive delay t incomb i/o register feedback delay t iofd t lac t ic t en t ftd t ioc
32 altera corporation max 9000 programmable logic device family data sheet tables 21 through 24 show timing for max 9000 devices. table 21. max 9000 external timing characteristics note (1) symbol parameter conditions speed grade unit -10 -15 -20 min max min max min max t pd1 row i/o pin input to row i/o pin output c1 = 35 pf (2) 10.0 15.0 20.0 ns t pd2 column i/o pin input to column i/o pin output c1 = 35 pf (2) epm9320a 10.8 ns epm9320 16.0 23.0 ns epm9400 16.2 23.2 ns epm9480 16.4 23.4 ns epm9560a 11.4 ns epm9560 16.6 23.6 ns t fsu global clock setup time for i/o cell 3.0 5.0 6.0 ns t fh global clock hold time for i/o cell 0.0 0.0 0.0 ns t fco global clock to i/o cell output delay c1 = 35 pf 1.0 (3) 4.8 1.0 (3) 7.0 1.0 (3) 8.5 ns t cnt minimum internal global clock period (4) 6.9 8.5 10.0 ns f cnt maximum internal global clock frequency (4) 144.9 117.6 100.0 mhz
altera corporation 33 max 9000 programmable logic device family data sheet table 22. max 9000 internal timing characteristics note (1) symbol parameter conditions speed grade unit -10 -15 -20 min max min max min max t lad logic array delay 3.5 4.0 4.5 ns t lac logic control array delay 3.5 4.0 4.5 ns t ic array clock delay 3.5 4.0 4.5 ns t en register enable time 3.5 4.0 4.5 ns t sexp shared expander delay 3.5 5.0 7.5 ns t pexp parallel expander delay 0.5 1.0 2.0 ns t rd register delay 0.5 1.0 1.0 ns t comb combinatorial delay 0.4 1.0 1.0 ns t su register setup time 2.4 3.0 4.0 ns t h register hold time 2.0 3.5 4.5 ns t pre register preset time 3.5 4.0 4.5 ns t clr register clear time 3.7 4.0 4.5 ns t ftd fasttrack drive delay 0.5 1.0 2.0 ns t lpa low-power adder (5) 10.0 15.0 20.0 ns
34 altera corporation max 9000 programmable logic device family data sheet table 23. ioc delays symbol parameter conditions speed grade unit -10 -15 -20 minmaxminmaxminmax t iodr i/o row output data delay 0.2 0.2 1.5 ns t iodc i/o column output data delay 0.4 0.2 1.5 ns t ioc i/o control delay (6) 0.5 1.0 2.0 ns t iord i/o register clock-to-output delay 0.6 1.0 1.5 ns t iocomb i/o combinatorial delay 0.2 1.0 1.5 ns t iosu i/o register setup time before clock 2.0 4.0 5.0 ns t ioh i/o register hold time after clock 1.0 1.0 1.0 ns t ioclr i/o register clear delay 1.5 3.0 3.0 ns t iofd i/o register feedback delay 0.0 0.0 0.5 ns t i nreg i/o input pad and buffer to i/o register delay 3.5 4.5 5.5 ns t i ncomb i/o input pad and buffer to row and column delay 1.5 2.0 2.5 ns t od1 output buffer and pad delay, slow slew rate = off, v ccio = 5.0 v c1 = 35 pf 1.8 2.5 2.5 ns t od2 output buffer and pad delay, slow slew rate = off, v ccio = 3.3 v c1 = 35 pf 2.3 3.5 3.5 ns t od3 output buffer and pad delay, slow slew rate = on, v ccio = 5.0 v or 3.3 v c1 = 35 pf 8.3 10.0 10.5 ns t xz output buffer disable delay c1 = 5 pf 2.5 2.5 2.5 ns t zx1 output buffer enable delay, slow slew rate = off, v ccio = 5.0 v c1 = 35 pf 2.5 2.5 2.5 ns t zx2 output buffer enable delay, slow slew rate = off, v ccio = 3.3 v c1 = 35 pf 3.0 3.5 3.5 ns t zx3 output buffer enable delay, slow slew rate = on, v ccio = 3.3 v or 5.0 v c1 = 35 pf 9.0 10.0 10.5 ns
altera corporation 35 max 9000 programmable logic device family data sheet notes to tables: (1) these values are specified under the max 9000 device recommended operating conditions, shown in table 15 on page 27 . (2) see application note 77 (understanding max 9000 timing) for more information on test conditions for t pd1 and t pd2 delays. (3) this parameter is a guideline that is sample-tested only. it is based on extensive device characterization. this parameter applies for both global and array clocking as well as both macrocell and i/o cell registers. (4) measured with a 16-bit loadable, enabled, up/down counter programmed in each lab. (5) the t lpa parameter must be added to the t local parameter for macrocells running in low-power mode . (6) the t row , t col, and t ioc delays are worst-case values for typical applications. post-compilation timing simulation or timing analysis is required to determine actual worst-case performance. power consumption the supply power (p) versus frequency ( f max ) for max 9000 devices can be calculated with the following equation: p = p int + p io = i ccint application note 74 (evaluating power for altera devices) . the i ccint value depends on the switching frequency and the application logic. the i ccint value is calculated with the following equation: i ccint = (a f max tog lc ) table 24. interconnect delays symbol parameter conditions speed grade unit -10 -15 -20 minmaxminmaxminmax t local lab local array delay 0.5 0.5 0.5 ns t row fasttrack row delay (6) 0.9 1.4 2.0 ns t col fasttrack column delay (6) 0.9 1.7 3.0 ns t din_d dedicated input data delay 4.0 4.5 5.0 ns t din_clk dedicated input clock delay 2.7 3.5 4.0 ns t din_clr dedicated input clear delay 4.5 5.0 5.5 ns t din_ioc dedicated input i/o register clock delay 2.5 3.5 4.5 ns t din_io dedicated input i/o register control delay 5.5 6.0 6.5 ns
36 altera corporation max 9000 programmable logic device family data sheet the parameters in this equation are shown below: mc ton = number of macrocells with the turbo bit option turned on, as reported in the max+plus ii report file ( .rpt ) mc dev = number of macrocells in the device mc used = number of macrocells used in the design, as reported in the max+plus ii report file f max = highest clock frequency to the device tog lc = average percentage of logic cells toggling at each clock (typically 12.5 % ) a, b, c = constants, shown in table 25 this calculation provides an i cc estimate based on typical conditions with no output load, using a typical pattern of a 16-bit, loadable, enabled up/down counter in each lab. actual i cc values should be verified during operation, because the measurement is sensitive to the actual pattern in the device and the environmental operating conditions. figure 15 shows typical supply current versus frequency for max 9000 devices. table 25. max 9000 i cc equation constants device constant a constant b constant c epm9320 0.81 0.33 0.056 epm9320a 0.56 0.31 0.024 epm9400 0.60 0.33 0.053 epm9480 0.68 0.29 0.064 epm9560 0.68 0.26 0.052 epm9560a 0.56 0.31 0.024
altera corporation 37 max 9000 programmable logic device family data sheet figure 15. i cc vs. frequency for max 9000 devices (part 1 of 2) 0 frequency (mhz) 1000 200 400 600 800 50 75 100 125 25 epm9320 118 mhz turbo frequency (mhz) 0 1000 200 400 600 800 50 75 100 125 25 epm9320a 144 mh z turbo 59 mhz 42 mhz non-turbo non-turbo typical i cc active (ma) typical i cc active (ma) 0 frequency (mhz) 42 mhz 42 mhz 1000 200 400 600 800 50 75 100 125 25 epm9400 118 mhz turbo 0 frequency (mhz) 1000 200 400 600 800 50 75 100 125 25 epm9480 118 mhz turbo non-turbo non-turbo typical i cc active (ma) typical i cc active (ma)
38 altera corporation max 9000 programmable logic device family data sheet figure 15. i cc vs. frequency for max 9000 devices (part 2 of 2) device pin-outs tables 26 through 29 show the dedicated pin names and numbers for each epm9320, epm9320a, epm9400, epm9480, epm9560, and epm9560a device package. 0 frequency (mhz) 42 mhz 59 mhz 1000 200 400 600 800 50 75 100 125 25 epm9560 118 mhz turbo 0 frequency (mhz) 1000 200 400 600 800 50 75 100 125 25 epm9560a 144 mhz turbo non-turbo non-turbo typical i cc active (ma) typical i cc active (ma) table 26. epm9320 & epm9320a dedicated pin-outs (part 1 of 2) note (1) pin name 84-pin plcc (2) 208-pin rqfp 280-pin pga (3) 356-pin bga din1 ( gclk1 ) 1 182 v10 ad13 din2 ( gclk2 ) 84 183 u10 af14 din3 ( gclr ) 13 153 v17 ad1 din4 ( goe )72 4 w2 ac24 tck 43 78 a9 a18 tms 55 49 d6 e23 tdi 42 79 c11 a13 tdo 30 108 a18 d3
altera corporation 39 max 9000 programmable logic device family data sheet gnd 6, 18, 24, 25, 48, 61, 67, 70 14, 20, 24, 31, 35, 41, 42, 43, 44, 46, 47, 66, 85, 102, 110, 113, 114, 115, 116, 118, 121, 122, 132, 133, 143, 152, 170, 189, 206 d4, d5, d16, e4, e5, e6, e15, e16, f5, f15, g5, g15, h5, h15, j5, j15, k5, k15, l5, l15, m5, m15, n5, n15, p4, p5, p15, p16, r4, r5, r15, r16, t4, t5, t16 a9, a22, a25, a26, b25, b26, d2, e1, e26, f2, g1, g25, g26, h2, j1, j25, j26, k2, l26, m26, n1, n25, p26, r2, t1, u2, u26, v1, v25, w25, y26, aa2, ab1, ab26, ac26, ae1, af1, af2, af4, af7, af20 vccint (5.0 v only) 14, 21, 28, 57, 64, 71 10, 19, 30, 45, 112, 128, 139, 148 d15, e8, e10, e12, e14, r7, r9, r11, r13, r14, t14 d26, f1, h1, k26, n26, p1, u1, w26, ae26, af25, af26 vccio (3.3 or 5.0 v) 15, 37, 60, 79 5, 25, 36, 55, 72, 91, 111, 127, 138, 159, 176, 195 d14, e7, e9, e11, e13, r6, r8, r10, r12, t13, t15 a1, a2, a21, b1, b10, b24, d1, h26, k1, m25, r1, v26, aa1, ac25, af5, af8, af19 no connect (n.c.) 29 6, 7, 8, 9, 11, 12, 13, 15, 16, 17, 18, 109, 140, 141, 142, 144, 145, 146, 147, 149, 150, 151 b6, k19, l2, l4, l18, l19, m1, m2, m3, m4, m16, m17, m18, m19, n1, n2, n3, n4, n16, n17, n18, n19, p1, p2, p3, p17, p18, p19, r1, r2, r3, r17, r18, r19, t1, t2, t3, t17, t18, t19, u1, u2, u3, u17, u18, u19, v1, v2, v19, w1 b4, b5, b6, b7, b8, b9, b11, b12, b13, b14, b15, b16, b18, b19, b20, b21, b22, b23, c4, c23, d4, d23, e4, e22, f4, f23, g4, h4, h23, j23, k4, l4, l23, n4, p4, p23, r3, r26, t2, t3, t4, t5, t22, t23, t24, t25, t26, u3, u4, u5, u22, u23, u24, u25, v2, v3, v4, v5, v22, v23, v24, w1, w2, w3, w4, w5, w22, w23, w24, y1, y2, y3, y4, y5, y22, y23, y24, y25, aa3, aa4, aa5, aa22, aa23, aa24, aa25, aa26, ab2, ab3, ab4, ab5, ab23, ab24, ab25, ac1, ac2, ac23, ad4, ad23, ae4, ae5, ae6, ae7, ae9, ae11, ae12, ae14, ae15, ae16, ae18, ae19, ae20, ae21, ae22, ae23 vpp (4) 56 48 c4 e25 total user i/o pins (5) 60 132 168 168 table 26. epm9320 & epm9320a dedicated pin-outs (part 2 of 2) note (1) pin name 84-pin plcc (2) 208-pin rqfp 280-pin pga (3) 356-pin bga
40 altera corporation max 9000 programmable logic device family data sheet notes: (1) all pins not listed are user i/o pins. (2) perform a complete thermal analysis before committing a design to this device package. see application note 74 (evaluating power for altera devices) . (3) epm9320a devices are not offered in this package. (4) during in-system programming, each device?s vpp pin must be connected to the 5.0-v power supply. during normal device operation, the vpp pin is pulled up internally and can be connected to the 5.0-v supply or left unconnected. (5) the user i/o pin count includes dedicated input pins and all i/o pins. notes: (1) all pins not listed are user i/o pins. (2) perform a complete thermal analysis before committing a design to this device package. see application note 74 (evaluating power for altera devices) for more information. (3) during in-system programming, each device?s vpp pin must be connected to the 5.0-v power supply. during normal device operation, the vpp pin is pulled up internally and can be connected to the 5.0-v supply or left unconnected. (4) the user i/o pin count includes dedicated input pins and all i/o pins. table 27. epm9400 dedicated pin-outs note (1) pin name 84-pin plcc (2) 208-pin rqfp 240-pin rqfp din1 ( gclk1 ) 2 182 210 din2 ( gclk2 ) 1 183 211 din3 ( gclr ) 12 153 187 din4 ( goe ) 74 4 234 tck 43 78 91 tms 54 49 68 tdi 42 79 92 tdo 31 108 114 gnd 6, 13, 20, 26, 27, 47, 60, 66, 69, 73 14, 20, 24, 31, 35, 41, 42, 43, 44, 46, 47, 66, 85, 102, 110, 113, 114, 115, 116, 118, 121, 122, 132, 133, 143, 152, 170, 189, 206 5, 14, 25, 34, 45, 54, 65, 66, 81, 96, 110, 115, 126, 127, 146, 147, 166, 167, 186, 200, 216, 229 vccint (5.0 v only) 16, 23, 30, 56, 63, 70 10, 19, 30, 45, 112, 128, 139, 148 4, 24, 44, 64, 117, 137, 157, 177 vccio (3.3 or 5.0 v) 17, 37, 59, 80 5, 25, 36, 55, 72, 91, 111, 127, 138, 159, 176, 195 15, 35, 55, 73, 86, 101, 116, 136, 156, 176, 192, 205, 220, 235 no connect (n.c.) e 6, 7, 8, 9, 11, 12, 13, 109, 144, 145, 146, 147, 149, 150, 151 1, 2, 3, 6, 7, 8, 9, 10, 11, 12, 13, 168, 169, 170, 171, 172, 173, 174, 175, 178, 179, 180, 181, 182, 183, 184, 185, 236, 237, 238, 239, 240 vpp (3) 55 48 67 total user i/o pins (4) 59 139 159
altera corporation 41 max 9000 programmable logic device family data sheet notes: (1) all pins not listed are user i/o pins. (2) during in-system programming, each device?s vpp pin must be connected to the 5.0-v power supply. during normal device operation, the vpp pin is pulled up internally and can be connected to the 5.0-v supply or left unconnected. (3) the user i/o pin count includes dedicated input pins and all i/o pins. table 28. epm9480 dedicated pin-outs note (1) pin name 208-pin rqfp 240-pin rqfp din1 ( gclk1 ) 182 210 din2 ( gclk2 ) 183 211 din3 ( gclr ) 153 187 din4 ( goe )4 234 tck 78 91 tms 49 68 tdi 79 92 tdo 108 114 gnd 14, 20, 24, 31, 35, 41, 42, 43, 44, 46, 47, 66, 85, 102, 110, 113, 114, 115, 116, 118, 121, 122, 132, 133, 143, 152, 170, 189, 206 5, 14, 25, 34, 45, 54, 65, 66, 81, 96, 110, 115, 126, 127, 146, 147, 166, 167, 186, 200, 216, 229 vccint (5.0 v only) 10, 19, 30, 45, 112, 128, 139, 148 4, 24, 44, 64, 117, 137, 157, 177 vccio (3.3 or 5.0 v) 5, 25, 36, 55, 72, 91, 111, 127, 138, 159, 176, 195 15, 35, 55, 73, 86, 101, 116, 136, 156, 176, 192, 205, 220, 235 no connect (n.c.) 6, 7, 8, 9, 109, 149, 150, 151 1, 2, 3, 178, 179, 180, 181, 182, 183, 184, 185, 236, 237, 238, 239, 240 vpp (2) 48 67 total user i/o pins (3) 146 175
42 altera corporation max 9000 programmable logic device family data sheet table 29. epm9560 & epm9560a dedicated pin-outs (part 1 of 2) note (1) pin name 208-pin rqfp 240-pin rqfp 280-pin pga (2) 304-pin rqfp (2) 356-pin bga din1 ( gclk1 ) 182 210 v10 266 ad13 din2 ( gclk2 ) 183 211 u10 267 af14 din3 ( gclr ) 153 187 v17 237 ad1 din4 ( goe ) 4 234 w2 296 ac24 tck 78 91 a9 114 a18 tms 49 68 d6 85 e23 tdi 79 92 c11 115 a13 tdo 108 114 a18 144 d3 gnd 14, 20, 24, 31, 35, 41, 42, 43, 44, 46, 47, 66, 85, 102, 110, 113, 114, 115, 116, 118, 121, 122, 132, 133, 143, 152, 170, 189, 206 5, 14, 25, 34, 45, 54, 65, 66, 81, 96, 110, 115, 126, 127, 146, 147, 166, 167, 186, 200, 216, 229 d4, d5, d16, e4, e5, e6, e15, e16, f5, f15, g5, g15, h5, h15, j5, j15, k5, k15, l5, l15, m5, m15, n5, n15, p4, p5, p15, p16, r4, r5, r15, r16, t4, t5, t16 13, 22, 33, 42, 53, 62, 73, 74, 102, 121, 138, 155, 166, 167, 186, 187, 206, 207, 226, 254, 273, 290 a9, a22, a25, a26, b25, b26, d2, e1, e26, f2, g1, g25, g26, h2, j1, j25, j26, k2, l26, m26, n1, n25, p26, r2, t1, u2, u26, v1, v25, w25, y26, aa2, ab1, ab26, ac26, ae1, af1, af2, af4, af7, af20 vccint (5.0 v only) 10, 19, 30, 45, 112, 128, 139, 148 4, 24, 44, 64, 117, 137, 157, 177 d15, e8, e10, e12, e14, r7, r9, r11, r13, r14, t14 12, 32, 52, 72, 157, 177, 197, 217 d26, f1, h1, k26, n26, p1, u1, w26, ae26, af25, af26 vccio (3.3 or 5.0 v) 5, 25, 36, 55, 72, 91, 111, 127, 138, 159, 176, 195 15, 35, 55, 73, 86, 101, 116, 136, 156, 176, 192, 205, 220, 235 d14, e7, e9, e11, e13, r6, r8, r10, r12, t13, t15 3, 23, 43, 63, 91, 108, 127, 156, 176, 196, 216, 243, 260, 279 a1, a2, a21, b1, b10, b24, d1, h26, k1, m25, r1, v26, aa1, ac25, af5, af8, af19
altera corporation 43 max 9000 programmable logic device family data sheet notes: (1) all pins not listed are user i/o pins. (2) epm9560a devices are not offered in this package. (3) during in-system programming, each device?s vpp pin must be connected to the 5.0-v power supply. during normal device operation, the vpp pin is pulled up internally and can be connected to the 5.0-v supply or left unconnected. (4) the user i/o pin count includes dedicated input pins and all i/o pins. no connect (n.c.) 109 e b6, w1 1, 2, 76, 77, 78, 79, 80, 81, 82, 83, 84, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 297, 298, 299, 300, 301, 302, 303, 304 b4, b5, b6, b7, b8, b9, b11, b12, b13, b14, b15, b16, b18, b19, b20, b21, b22, b23, c4, c23, d4, d23, e4, e22, f4, f23, g4, h4, h23, j23, k4, l4, l23, n4, p4, p23, t4, t23, u4, v4, v23, w4, y4, aa4, aa23, ab4, ab23, ac23, ad4, ad23, ae4, ae5, ae6, ae7, ae9, ae11, ae12, ae14, ae15, ae16, ae18, ae19, ae20, ae21, ae22, ae23 vpp (3) 48 67 c4 75 e25 tot al us er i/o pins (4) 153 191 216 216 216 table 29. epm9560 & epm9560a dedicated pin-outs (part 2 of 2) note (1) pin name 208-pin rqfp 240-pin rqfp 280-pin pga (2) 304-pin rqfp (2) 356-pin bga
copyright ? 2003 altera corporation. all rights reserved. altera, the programmable solutions company, th e stylized altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of alte ra corporation in the u.s. and other countries. all other product or service names are the property of the ir respective holders. altera products are protected under numerous u.s. and foreign patents and pendin g applications, maskwork rights, and copyrights. altera warrants performance of its semiconductor products to current specifications in accordance with altera?s standard warranty, but reserves the right to make chang es to any products and services at any time without notice. altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera corporation. altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 1 01 innovation drive s an jose, ca 95134 ( 408) 544-7000 h ttp://www.altera.com a pplications hotline: ( 800) 800-epld c ustomer marketing: ( 408) 544-7104 l iterature services: l it_req@altera.com max 9000 programmable logic device family data sheet 44 altera corporation printed on recycled paper. revision history information contained in the max 9000 programmable logic device family data sheet version 6.5 supersedes information published in previous versions. version 6.5 version 6.6 of the max 9000 programmable logic device family data sheet contains the following change: added tables 7 through 9 . added ?programming sequence? on page 20 and ?programming times? on page 20 version 6.4 version 6.4 of the max 9000 programmable logic device family data sheet contains the following change: updated text on page 23 . version 6.3 version 6.3 of the max 9000 programmable logic device family data sheet contains the following change: added note (7) to table 16 .
altera corporation 45 max 9000 programmable logic device family data sheet
46 altera corporation max 9000 programmable logic device family data sheet
altera part number search literature licensing buy on-line download home | products | support | system solutions | technology center | education & events | corporate | buy on-line results for: epm9320* 11 part numbers found and 9 obsolete part numbers found max 9000 device family max 9000 datasheet max 9000 literature part number format buying altera devices part number device pin & package temperature speeds options epm9320alc84-10 epm9320a 84 pin plcc commercial ( 0 to 90c) -10 none epm9320ali84-10 epm9320a 84 pin plcc industrial ( -40 to 105c) -10 none epm9320arc208-10 epm9320a 208 pin rqfp commercial ( 0 to 90c) -10 none epm9320ari208-10 epm9320a 208 pin rqfp industrial ( -40 to 105c) -10 none epm9320bc356-20 epm9320 356 pin bga commercial ( 0 to 90c) -20 none epm9320lc84-15 epm9320lc84-20 epm9320 84 pin plcc commercial ( 0 to 90c) -15, -20 none epm9320li84-20 epm9320 84 pin plcc industrial ( -40 to 105c) -20 none epm9320rc208-15 epm9320rc208-20 epm9320 208 pin rqfp commercial ( 0 to 90c) -15, -20 none epm9320ri208-20 epm9320 208 pin rqfp industrial ( -40 to 105c) -20 none your search for epm9320* found 9 obsolete part numbers. obsolete part numbers part number format buying altera devices part number last order date last ship date replacement notes epm9320abc356-10 2/28/02 8/31/02 contact altera pdn0106 epm9320bc356-15 2/28/02 8/31/02 contact altera pdn0106 epm9320gc280-15 2/28/02 8/31/02 contact altera pdn0106 epm9320gc280-20 2/28/02 8/31/02 contact altera pdn0106 epm9320lc84-20h 2/28/02 8/31/02 contact altera pdn0106 http://www.altera.com/cgi-bin/devsearch.pl?searc...=corp&qt=epm9320*&scope=0&submit.x=18&submit.y=4 (1 of 2) [9/2/2004 3:14:16 pm]
altera part number search epm9320rc208-15c 8/31/01 2/28/02 contact altera pdn0106 epm9320rc208-15f 5/31/02 11/30/02 no direct replacement pdn 0117 epm9320rc208-20c 8/31/01 2/28/02 contact altera pdn0106 epm9320ri208-20c 8/31/01 2/28/02 contact altera pdn0106 advanced help please give us feedback sign up for e-mail updates home | products | support | system solutions | technology center | education & events | corporate | buy on-line contact us | new user | site map | privacy | legal notice copyright ? 1995-2004 altera corporation, 101 innovation drive, san jose, california 95134, usa http://www.altera.com/cgi-bin/devsearch.pl?searc...=corp&qt=epm9320*&scope=0&submit.x=18&submit.y=4 (2 of 2) [9/2/2004 3:14:16 pm]
altera part number search literature licensing buy on-line download home | products | support | system solutions | technology center | education & events | corporate | buy on-line results for: epm9480* 4 part numbers found and 4 obsolete part numbers found max 9000 device family max 9000 datasheet max 9000 literature part number format buying altera devices part number device pin & package temperature speeds options epm9480rc208-15 epm9480rc208-20 epm9480 208 pin rqfp commercial ( 0 to 90c) -15, -20 none epm9480rc240-15 epm9480rc240-20 epm9480 240 pin rqfp commercial ( 0 to 90c) -15, -20 none your search for epm9480* found 4 obsolete part numbers. obsolete part numbers part number format buying altera devices part number last order date last ship date replacement notes epm9480rc208-15c 8/31/01 2/28/02 contact altera pdn0106 epm9480rc208-20c 8/31/01 2/28/02 contact altera pdn0106 epm9480rc240-15c 8/31/01 2/28/02 contact altera pdn0106 epm9480rc240-20c 8/31/01 2/28/02 contact altera pdn0106 advanced help please give us feedback sign up for e-mail updates home | products | support | system solutions | technology center | education & events | corporate | buy on-line contact us | new user | site map | privacy | legal notice copyright ? 1995-2004 altera corporation, 101 innovation drive, san jose, california 95134, usa http://www.altera.com/cgi-bin/devsearch.pl?searchtext=&docsetconstraints=&col=corp&qt=epm9480*&scope=0 [9/2/2004 3:14:26 pm]
altera part number search literature licensing buy on-line download home | products | support | system solutions | technology center | education & events | corporate | buy on-line results for: epm9560* 13 part numbers found and 19 obsolete part numbers found max 9000 device family max 9000 datasheet max 9000 literature part number format buying altera devices part number device pin & package temperature speeds options epm9560abc356-10 epm9560a 356 pin bga commercial ( 0 to 90c) -10 none epm9560arc208-10 epm9560a 208 pin rqfp commercial ( 0 to 90c) -10 none epm9560arc240-10 epm9560a 240 pin rqfp commercial ( 0 to 90c) -10 none epm9560ari208-10 epm9560a 208 pin rqfp industrial ( -40 to 105c) -10 none epm9560ari240-10 epm9560a 240 pin rqfp industrial ( -40 to 105c) -10 none epm9560rc208-15 epm9560rc208-20 epm9560 208 pin rqfp commercial ( 0 to 90c) -15, -20 none epm9560rc240-15 epm9560rc240-20 epm9560 240 pin rqfp commercial ( 0 to 90c) -15, -20 none epm9560rc304-15 epm9560 304 pin rqfp commercial ( 0 to 90c) -15 none epm9560ri208-20 epm9560 208 pin rqfp industrial ( -40 to 105c) -20 none epm9560ri240-20 epm9560 240 pin rqfp industrial ( -40 to 105c) -20 none epm9560ri304-20 epm9560 304 pin rqfp industrial ( -40 to 105c) -20 none your search for epm9560* found 19 obsolete part numbers. obsolete part numbers part number format buying altera devices part number last order date last ship date replacement notes epm9560arc304-10f 2/28/02 8/31/02 contact altera pdn0106 epm9560bc356-15 2/28/02 8/31/02 contact altera pdn0106 http://www.altera.com/cgi-bin/devsearch.pl?search...=&docsetconstraints=&col=corp&qt=epm9560*&scope=0 (1 of 2) [9/2/2004 3:14:31 pm]
altera part number search epm9560bc356-20 5/31/02 11/30/02 no direct replacement pdn 0117 epm9560gc280-15 2/28/02 8/31/02 contact altera pdn0106 epm9560gc280-20 2/28/02 8/31/02 contact altera pdn0106 epm9560rc208-15c 8/31/01 2/28/02 contact altera pdn0106 epm9560rc208-20c 8/31/01 2/28/02 contact altera pdn0106 epm9560rc240-15c 8/31/01 2/28/02 contact altera pdn0106 epm9560rc240-20c 8/31/01 2/28/02 contact altera pdn0106 epm9560rc304-15c 8/31/01 2/28/02 contact altera pdn0106 epm9560rc304-15f 2/28/02 8/31/02 contact altera pdn0106 epm9560rc304-20 2/28/02 8/31/02 contact altera pdn0106 epm9560rc304-20c 8/31/01 2/28/02 contact altera pdn0106 epm9560ri240-20c 8/31/01 2/28/02 contact altera pdn0106 epm9560ri304-20c 8/31/01 2/28/02 contact altera pdn0106 epm9560wc208-15 12/31/96 3/31/97 epm9560rc208-15 pdn 9618 epm9560wc208-15c 12/31/96 3/31/97 epm9560rc208-15c pdn 9618 epm9560wc208-20 12/31/96 3/31/97 epm9560rc208-20 pdn 9618 epm9560wc208-20c 12/31/96 3/31/97 epm9560rc208-20c pdn 9618 advanced help please give us feedback sign up for e-mail updates home | products | support | system solutions | technology center | education & events | corporate | buy on-line contact us | new user | site map | privacy | legal notice copyright ? 1995-2004 altera corporation, 101 innovation drive, san jose, california 95134, usa http://www.altera.com/cgi-bin/devsearch.pl?search...=&docsetconstraints=&col=corp&qt=epm9560*&scope=0 (2 of 2) [9/2/2004 3:14:31 pm]
altera part number search literature licensing buy on-line download home | products | support | system solutions | technology center | education & events | corporate | buy on-line results for: epm9400* 4 part numbers found and 6 obsolete part numbers found max 9000 device family max 9000 datasheet max 9000 literature part number format buying altera devices part number device pin & package temperature speeds options epm9400rc208-15 epm9400rc208-20 epm9400 208 pin rqfp commercial ( 0 to 90c) -15, -20 none epm9400rc240-15 epm9400rc240-20 epm9400 240 pin rqfp commercial ( 0 to 90c) -15, -20 none your search for epm9400* found 6 obsolete part numbers. obsolete part numbers part number format buying altera devices part number last order date last ship date replacement notes epm9400lc84-15 2/28/02 8/31/02 contact altera pdn0106 epm9400lc84-20 2/28/02 8/31/02 contact altera pdn0106 epm9400rc208-15c 8/31/01 2/28/02 contact altera pdn0106 epm9400rc208-20c 8/31/01 2/28/02 contact altera pdn0106 epm9400rc240-15c 8/31/01 2/28/02 contact altera pdn0106 epm9400rc240-20c 8/31/01 2/28/02 contact altera pdn0106 advanced help please give us feedback sign up for e-mail updates home | products | support | system solutions | technology center | education & events | corporate | buy on-line contact us | new user | site map | privacy | legal notice copyright ? 1995-2004 altera corporation, 101 innovation drive, san jose, california 95134, usa http://www.altera.com/cgi-bin/devsearch.pl?searchtext=&docsetconstraints=&col=corp&qt=epm9400*&scope=0 [9/2/2004 3:14:21 pm]

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